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Computer Organization and Architecture (Complete Playlist) — Free Course | SyncStudy

Course Syllabus

Complete Lecture Curriculum (66 Lectures)

Full index of topics and video runtimes included in this course.

Total: 9h 39m

01
L-1.1: Computer Organization and Architecture Syllabus Discussion for GATE and UGC NTA NET
13:40
Lesson
02
L-1.2: Von Neumann's Architecture | Stored Memory Concept in Computer Architecture
9:40
Lesson
03
L-1.3:Various General Purpose Registers in Computer Organization and Architecture
15:11
Lesson
04
L-1.4:Types of Buses (Address, Data and Control) in Computer Organization and Architecture
7:59
Lesson
05
L-1.5: Common bus system using multiplexer | Computer organization and Architecture
11:26
Lesson
06
L-1.6: Common Bus system| How basic computer works
19:11
Lesson
07
L-1.7: Types of Instructions in General Purpose Computer | Computer Organization and Architecture
5:11
Lesson
08
L-1.8: Data Transfer Instructions in Computer Organisation and Architecture
7:45
Lesson
09
L-1.9: Arithmetic Instructions(Data Manipulation) in Computer Organisation and Architecture
8:44
Lesson
10
L-1.10: Logical Instructions(Data Manipulation) in Computer Organisation and Architecture
9:12
Lesson
11
L-1.11: Shift Instructions(Data Manipulation) in Computer Organisation and Architecture
13:28
Lesson
12
L-1.12: Program Control Instructions(Types of Control Instructions) | Computer Organization
10:51
Lesson
13
L-1.13: What is Instruction Format | Understand Computer Organisation with Simple Story
10:40
Lesson
14
L-1.14: Question on Instruction Format | Computer Organization | UGC NTA NET June 2021
8:51
Lesson
15
L-1.15: Single Accumulator CPU Organisation | Single Address Instructions in Computer Organisation
8:03
Lesson
16
L-1.16: General Register CPU Organisation | Two and Three Address Instructions | COA
7:19
Lesson
17
L-1.17: Register Stack Organisation | Zero Address Instructions | COA
11:50
Lesson
18
L-1.18:Memory Stack Organisation | Memory stack Vs Register stack | COA
6:03
Lesson
19
L-2.1: What is Addressing Mode | Various Types of Addressing Modes | COA
11:45
Lesson
20
L-2.2: Implied Addressing Mode | Computer Organisation and Architecture
4:56
Lesson
21
L-2.3: Immediate Addressing Mode | Computer Organisation and Architecture
6:36
Lesson
22
L-2.4: Register Mode | Addressing Mode | Computer Organisation and Architecture
4:39
Lesson
23
L-2.5: Register Indirect Mode | Addressing Modes | Computer Organisation and Architecture
6:22
Lesson
24
L-2.6: Auto Increment and Decrement Addressing Modes | Computer Organisation and Architecture
6:51
Lesson
25
L-2.7: Direct Addressing Mode || Computer Organization and Architecture
4:51
Lesson
26
L-2.8: Indirect Addressing Mode | Computer Organisation and Architecture
6:05
Lesson
27
`L-2.9: Relative Addressing Mode || Computer Organisation and Architecture
7:08
Lesson
28
L-2.10: Base Register Addressing Mode || Computer Organisation and Architecture
6:58
Lesson
29
L-2.11: Indexed Addressing Mode || Computer Organisation and Architecture
4:05
Lesson
30
L-2.12: Question on Addressing Modes | Computer Organization
4:46
Lesson
31
L-2.13: RISC vs CISC | Computer Organization & Architecture
8:22
Lesson
32
L-3.1: Memory Hierarchy in Computer Architecture | Access time, Speed, Size, Cost | All Imp Points
7:32
Lesson
33
L-3.2: Independent vs Hierarchical Memory Organization | 2-Level Memory Organization
10:04
Lesson
34
L-3.3: 3-Level Memory Organisation || Computer Organisation and Architecture
8:19
Lesson
35
L-3.4: GATE 2004 Question on 3-Level Memory Organisation || Computer Organisation and Architecture
5:50
Lesson
36
L-3.5: What is Cache Mapping || Cache Mapping techniques || Computer Organisation and Architecture
7:40
Lesson
37
L-3.6: Direct Mapping with Example in Hindi | Cache Mapping | Computer Organisation and Architecture
22:03
Lesson
38
L-3.7: GATE 2005 Question on Direct Mapping | Cache Mapping Questions | Computer Organization
7:22
Lesson
39
L-3.8: Fully Associative Mapping with examples in Hindi | Cache Mapping | Computer Organisation
9:56
Lesson
40
L-3.9: Advantages and Disadvantages of Direct Mapping | Cache Mapping | Computer Organisation
9:08
Lesson
41
L-3.10: Set Associative Mapping with Examples in Hindi | Cache Mapping | Computer Organisation
10:52
Lesson
42
L-3.11: Locality of Reference in Cache Memory | Spatial Vs Temporal Locality | Computer Organization
8:47
Lesson
43
L-3.12: Cache Replacement Algorithms in Computer Organisation and Architecture
5:35
Lesson
44
L-3.13: LRU (Least Recently Used) Cache Replacement Algorithm | Computer Organisation & Architecture
8:58
Lesson
45
L-3.14: Gate 2014 Question on Set Associative Cache Mapping | Computer Organisation and Architecture
8:16
Lesson
46
L-3.15: FIFO Cache Replacement Policy with example | Computer Organisation and Architecture
9:05
Lesson
47
L-3.16: LRU(least recently used ) Cache Replacement Policy | Computer Organisation and Architecture
7:31
Lesson
48
L-4.1: Pipelining with real life example| Need of Pipelining | COA
8:18
Lesson
49
L-4.2: Pipelining Introduction and structure | Computer Organisation
3:54
Lesson
50
L-4.3: Pipelining Vs Non-Pipelining | Instruction Execution | Speedup, Efficiency, Utilization | COA
13:04
Lesson
51
L-4.4: Stage Delay in Pipeline | Previous Year GATE Question | Computer Organisation & Architecture
10:54
Lesson
52
L-4.5: Numerical Question on Pipelining | Previous year GATE Question | COA
4:25
Lesson
53
L-4.6: What is Hazard in Pipelining | various types of Hazards | computer Architecture
10:29
Lesson
54
L-4.7: Structural Hazards in Pipelining | Types of Hazards with Example in Hindi
9:33
Lesson
55
L-4.8: Control Hazards in Pipelining | Types of Hazards with Example in Hindi
13:52
Lesson
56
L-4.9: What is Read After Write(RAW) Hazards| Data Hazard in Pipelining with Example in Hindi | COA
8:05
Lesson
57
L-4.10: Write After Read Hazard with Example | Data Hazards| Computer Organization and Architecture
9:19
Lesson
58
L-4.11: Write After Write Hazard | Data Hazards in Pipelining | Computer Organization &&Architecture
5:51
Lesson
59
L-4.12: Register Renaming in Computer Organization | Data Hazard
9:56
Lesson
60
L-4.13: Operand Forwarding in Computer Organization & Architecture | Data Hazard
11:11
Lesson
61
I/O Interface in Computer Organization
5:45
Lesson
62
Interrupts in 8085 microprocessor | Types of Interrupts in Computer Organization
9:37
Lesson
63
Daisy Chaining in Priority Interrupt | Priority Based Interrupt in I/O Organization
6:35
Lesson
64
Parallel priority interrupt | I/O organization
7:38
Lesson
65
Question on Interrupt Handling(I/O organization) | Computer Organization | UGC NTA NET June 2021
8:49
Lesson
66
Question on DMA (Direct Memory Access) | Input/Output Organization| COA | UGC NTA NET June 2021
7:01
Lesson

Computer Organization and Architecture (Complete Playlist)

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