Digital Design with Verilog

Digital Design with Verilog: [Introduction Video]

Lec 1: Introduction to Digital Design with Verilog

Lec 2: Switching Algebra

Lec 3: Canonical Forms of Switching Functions

Lec 4: Number Systems

Lec 5: Binary Arithmetic

Lec 6: Binary Codes

Lec 7: Error Detection and Corrections Codes

Lec 8: Minimization of Switching functions-Karnaugh Map

Lec 9: Karnaugh Map

Lec 10: Minimization of Switching functions-Properties

Lec 11: Quine-McCluskey Method

Lec 12: Quine-McCluskey Method-Prime Implication Chart

Lec 13: ESPRESSO-Heuristic Based Switching Function Minimization

Lec 14: Multi-level Logic Minimization

Lec 15: Multi-level Logic Minimization-Kernels Extraction

Lec 16: Digital Circuits Modelling using Verilog

Lec 17: Modelling Techniques in Verilog

Lec 18: Behavioral Modelling in Verilog

Lec 19: Digital System Design using Verilog

Lec 20: Testbench in Verilog

Lec 21: Code Conversion, Parity Bit Generator

Lec 22: Comparator, Multiplexer

Lec 23: Encoder, Decoder

Lec 24: Ripple Carry Adder, Carry Look ahead Adder

Lec 25: Adder/Subtractor

Lec 26: BCD Adder, Multiplier

Lec 27:Latch/Storage Design

Lec 28:Flipflop Design, Characteristics of Flipflop

Lec 29:Flipflop, Register and Memory

Lec 30: Digital Counter

Lec 31: Finite State Machine Design and Implementation with many Examples

Lec 32: FSM Completeness and Correctness

Lec 33: Sync Counter using FSM, Implementation using different FFs and Comparision of types of FSM

Lec 34: FSM State Optimization using Row Matching and Partitioning Methods

Lec 35: State Optimization using Implication chart and State Encoding

Lec 38: ASM Data Path Inference and Control Path Generation

Lec 39: Sequential Multplier the Classic Example of RTL Design

Lec 40: Introduction to FPGA and Design Flow

Lec 41: Introduction to Electronic Design Automation

Lec 36: RTL Design, Introduction to ASM (Algorithmic State Machine)

Lec 37:RTL/ASM Design Examples and Implementation