Hardware Modelling using Verilog - IIT Kharagpur - Prof. Indranil Sengupta

Prof. Indranil Sen Gupta

Introduction

Design Representation

Getting Started with Verilog

VLSI Design Styles (Part 1)

VLSI Design Styles (Part 2)

VERILOG LANGUAGE FEATURES (PART 1)

VERILOG LANGUAGE FEATURES (PART 2)

VERILOG LANGUAGE FEATURES (PART 3)

VERILOG OPERATORS

VERILOG MODELING EXAMPLES

VERILOG MODELING EXAMPLES (Contd)

VERILOG DESCRIPTION STYLES

PROCEDURAL ASSIGNMENT

PROCEDURAL ASSIGNMENT (Contd.)

PROCEDURAL ASSIGNMENT (EXAMPLES)

BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 1)

BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)

BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 3)

BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 4)

USER DEFINED PRIMITIVES

VERILOG TEST BENCH

WRITING VERILOG TEST BENCHES

MODELING FINITE STATE MACHINES

MODELING FINITE STATE MACHINES (Contd.)

DATAPATH AND CONTROLLER DESIGN (PART 1)

DATAPATH AND CONTROLLER DESIGN (PART 2)

DATAPATH AND CONTROLLER DESIGN (PART 3)

SYNTHESIZABLE VERILOG

SOME RECOMMENDED PRACTICES

MODELING MEMORY

MODELING REGISTER BANKS

BASIC PIPELINING CONCEPTS

PIPELINE MODELING (PART 1)

PIPELINE MODELING (PART 2)

SWITCH LEVEL MODELING (PART 1)

SWITCH LEVEL MODDELING (PART 2)

PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 1)

PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 2)

PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 3)

VERILOG MODELING OF THE PROCESSOR (PART 1)

VERILOG MODELING OF THE PROCESSOR (PART 1)